A PLL circuit has a phase comparator which compares the phases of an input reference clock and a feedback clock obtained by division by N (where N is a positive number) of the output clock of the PLL circuit; a charge pump circuit which generates a current according to the phase difference; a loop filter which integrates this current; an oscillation circuit which generates an output clock at a frequency according to the control voltage output by the loop filter; and a frequency divider which divides this output clock by N and generates a feedback clock. In general, the output clock is a high-speed clock having a frequency which is N times the reference clock.
PLL circuits generate an output clock having a phase coinciding with or matched to the phase of the reference clock, and are widely used when high-frequency clocks matched to the timing of a reference clock are needed.
PLL circuits are discussed in Japanese Patent Laid-open No. 2006-345512, Japanese Patent Laid-open No. 2006-333489, and Japanese Patent Laid-open No. 10-233681.
Ideally in a PLL circuit, the control voltage and the output clock of the oscillation circuit are constant in a state in which the phases of the reference clock and feedback clock coincide. This state is the locked state of the PLL circuit.
However, due to variation in processes to manufacture integrated circuit devices, variation in temperature, variation in power supply voltage, and diverse other variation, even when in the locked state, there are cases in which the phases of the reference clock and feedback clock are steadily shifted. Such a phase shift is called a steady-state phase error.
When the lock state is entered while this steady-state phase error is occurring, the shift between the output clock phase and the reference clock phase remains unchanged, and the output clock timing does not agree with the reference clock timing. Consequently, when for example using the output clock as a sampling clock for input data matched to the timing of the reference clock, if the data rate of the input data is fast, sampling occurs with erroneous timing, and erroneous input data is captured.